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博士班
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學年度 |
博士生姓名 |
期刊與研討會論文 |
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97級 |
吳桐其 |
1. Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, and Tung-Chi Wu, “Imprecise 4-2 Compressor Design Used in Image Processing Applications,” IET Circuits, Devices & Systems, Vol. 13, No. 6, pp. 848-856, Sep. 2019. 5-year Impact Factor: 1.319
2. Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “An Imprecise 4-2 Compressor Design with Low Error Rate,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21), Yokohama, Japan, Apr. 18-20, 2018.
3. Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Radix-4 Adder Design with Refined Carry,” in Proc. IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, Aug. 7-10, 2017, pp. 300-304.
4. Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A High-Speed Radix-4 Adder Design,”in Proc. The 28th VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 1-4, 2017.
5. Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Mask Vertical Control TCAM for Network Router,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct. 25-28, 2016, pp. 469-472.
6. Yu-Cheng Cheng, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Pre-encoded Radix-4 Booth Multiplier,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIX), Yokohama, Japan, Apr. 20-22, 2016.
7. Yi-Fong Lin, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A Novel Imprecise Compressor Design Used in DSP Multiplier,” in Proc. The 26th VLSI Design/ CAD Symposium, Hualien, Taiwan, Aug. 4-7, 2015.
8. Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Router Design Using Vertical Gating Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Yokohama, Japan, Apr. 13-15, 2015.
9. Yen-Jen Chang and Tung-Chi Wu, “Master-Slave Match Line Design for Low Power Content Addressable Memory,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 9, pp. 1740-1749, Aug. 2014. Impact Factor: 1.245
10. Ya-chun Lin, Yen-Jen Chang, and Tung-Chi Wu, “Low-Power Content-Addressable Memory Design Using a Double Match-Line (DML) Architecture”, in Proc. IEEE 56th International Midwest Symposium on Circuits & Systems (MWSCAS), Ohio, USA, Aug. 4-7, 2013, pp. 425-428.
11. Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Charge Balance Tag Memory Design Used in TLB,” inProc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Yokohama, Japan, Apr. 17-19, 2013.
12. Guan-Lin Jiang, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Multiplier with Alternative Bypassing Implementation,” in Proc. International Conference on Embedded Systems and Applications (ESA’12), Las Vegas, USA, July 16-19, 2012, pp. 77-82.
13. Shuang-An Tseng, Tung-Chi Wu, and Yen-Jen Chang, “A Low Power SRAM Design with Segmented Stacking Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XV), Yokohama, Japan, Apr. 18-20, 2012.
14. 13. Yen-Jen Chang and Tung-Chi Wu, “A low-power TCAM design using mask-aware match-line (MAML) technique,” in Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI’11), Lausanne, Switzerland, May 2-4, 2011, pp. 109-114. |
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101級 |
鄭有成 |
1. Yen-Jen Chang, Kun-Lin Tsai, and Yu-Cheng Cheng, “Data Retention based Low Leakage Power TCAM for Network Packet Routing,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), Vol. 68, No. 2, pp. 757-761, Feb 2021. 5-year Impact Factor: 2.697
2. Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao, “A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism,” IEEE Access, Vol. 8, pp. 114842-114853, June 2020. 5-year Impact Factor: 4.076
3. Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng, and Meng-Rong Lu, “Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment,” Computers and Electrical Engineering, Vol. 81, pp. 1-11, Jan. 2020. 5-year Impact Factor: 2.337
4. Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, and Tung-Chi Wu, “Imprecise 4-2 Compressor Design Used in Image Processing Applications,” IET Circuits, Devices & Systems, Vol. 13, No. 6, pp. 848-856, Sep. 2019. 5-year Impact Factor: 1.319
5. Yu-Cheng Cheng, Yen-Yuan Wang, and Yen-Jen Chang, “A Low Power Radix-4 Booth Multiplier with Precise Operand Exchange Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), Yokohama, Japan, Apr. 17-19, 2019.
6. Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “An Imprecise 4-2 Compressor Design with Low Error Rate,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21), Yokohama, Japan, Apr. 18-20, 2018.
7. Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Radix-4 Adder Design with Refined Carry,” in Proc. IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, Aug. 7-10, 2017, pp. 300-304.
8. Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A High-Speed Radix-4 Adder Design,”in Proc. The 28th VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 1-4, 2017.
9. Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Mask Vertical Control TCAM for Network Router,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct. 25-28, 2016, pp. 469-472.
10. Yu-Cheng Cheng, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Pre-encoded Radix-4 Booth Multiplier,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIX), Yokohama, Japan, Apr. 20-22, 2016.
11. Yi-Fong Lin, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A Novel Imprecise Compressor Design Used in DSP Multiplier,” in Proc. The 26th VLSI Design/ CAD Symposium, Hualien, Taiwan, Aug. 4-7, 2015.
12. Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Router Design Using Vertical Gating Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Yokohama, Japan, Apr. 13-15, 2015.
13. Kun-Lin Tsai, Yen-Jen Chang and Yu-Cheng Cheng, “Automatic Charge Balancing Content Addressable Memory with Self-control Mechanism,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 10, pp. 2834-2841, Sep. 2014. Impact Factor: 2.403
14. Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Charge Balance Tag Memory Design Used in TLB,” inProc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Yokohama, Japan, Apr. 17-19, 2013. |
碩士班
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學年度 |
研究生姓名 |
期刊與研討會論文 |
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93級 |
廖元宏 |
1. Yen-Jen Chang and Yuan-Hong Liao, “Hybrid-Type CAM Design for Both Power and Performance Efficiency”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 8, pp.965-974, Aug. 2008. Impact Factor: 1.373
2. Yen-Jen Chang, Yuan-Hong Liao, and Shanq-Jang Ruan, “Improve CAM Power Efficiency Using Decoupled Match Line Scheme,” in Proc. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE’07), Nice, France, Apr. 16-20, 2007, pp. 1-6. |
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96級 |
楊晉維 |
1. Jin-Wei Yang and Yen-Jen Chang, “Low Power Selected Gating Frame Buffer (SGFB) Design,” in Proc. International Conference on Embedded Systems and Applications (ESA’09), Las Vegas, USA, July 13-16, 2009, pp. 140-145. |
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96級 |
鄭永鋒 |
1. Yung-Feng Cheng and Yen-Jen Chang, “A Novel High Performance Ternary CAM (TCAM) For LPM,” in Proc.International Conference on Embedded Systems and Applications (ESA’09), Las Vegas, USA, July 13-16, 2009, pp. 22-27. |
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96級 |
姜彥廷 |
1. Yen-Ting Chiang and Yen-Jen Chang, “A New SRAM Cell Design for Both Power and Performance Efficiency,”in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’09), Hsinchu, Taiwan, Aug. 31-Sep. 2, 2009, pp.13-19. |
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96級 |
蔡翔任 |
1. Yen-Jen Chang, Kun-Lin Tsai, and Hsiang-Jen Tsai, “Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.60, No. 6, pp. 1478-1486, June 2013. Impact Factor: 2.303
2. Hsiang-Jen Tsai and Yen-Jen Chang, “Low Power Ternary CAM (TCAM) Design Using Mask Gating,” inProc. IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS ‘09), Delft, Netherlands, Sep. 9-11, 2009. |
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97級 |
黃劭瑋 |
1. Shao-Wei Huang and Yen-Jen Chang, “A Full Parallel Priority Encoder Design Used in Comparator,” in Proc.IEEE 53rd International Midwest Symposium on Circuits & Systems (MWSCAS), Seattle, USA, Aug. 1-4, 2010, pp. 877-880. |
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97級 |
盧翔裕 |
1. Yen-Jen Chang and Hsiang-Yu Lu, “Improving the Performance of Port Range Check for Network Packet Filter,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 19, No. 1, pp. 3:1-3:21, Dec. 2013. Impact Factor: 0.520
2. Hsiang-Yu Lu and Yen-Jen Chang, “A High Performance Range Matching Circuit Design for Packet Filter,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIII), Yokohama, Japan, Apr. 14-16, 2010, pp. 183. |
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98級 |
劉信均 |
1. Hsin-Chun Liu, and Yen-Jen Chang, “A Low Power Radix-4 Booth Multiplier Design,” in Proc. The 22nd VLSI Design/ CAD Symposium, Yunlin, Taiwan, Aug. 1-4, 2011, pp. 432-435. |
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98級 |
江冠霖 |
1. Guan-Lin Jiang, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Multiplier with Alternative Bypassing Implementation,” in Proc. International Conference on Embedded Systems and Applications (ESA’12), Las Vegas, USA, July 16-19, 2012, pp. 77-82.
2. Guan-Lin Jiang and Yen-Jen Chang, “A New Bypassing Design for Low Power Multiplier,” in Proc. The 22nd VLSI Design/ CAD Symposium, Yunlin, Taiwan, Aug. 1-4, 2011, pp. 129-132. |
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99級 |
曾雙安 |
1. Shuang-An Tseng, Tung-Chi Wu, and Yen-Jen Chang, “A Low Power SRAM Design with Segmented Stacking Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XV), Yokohama, Japan, Apr. 18-20, 2012. |
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100級 |
林雅純 |
1. Ya-chun Lin, Yen-Jen Chang, and Tung-Chi Wu, “Low-Power Content-Addressable Memory Design Using a Double Match-Line (DML) Architecture”, in Proc. IEEE 56th International Midwest Symposium on Circuits & Systems (MWSCAS), Ohio, USA, Aug. 4-7, 2013, pp. 425-428. |
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100級 |
鄭有成 |
1. Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Charge Balance Tag Memory Design Used in TLB,” inProc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVI), Yokohama, Japan, Apr. 17-19, 2013. |
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101級 |
呂孟蓉 |
1. Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng, and Meng-Rong Lu, “Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment,” Computers and Electrical Engineering, Vol. 81, pp. 1-11, Jan. 2020. 5-year Impact Factor: 2.337 |
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101級 |
陳金昊 |
1. Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Mask Vertical Control TCAM for Network Router,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct. 25-28, 2016, pp. 469-472.
2. Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Router Design Using Vertical Gating Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XVIII), Yokohama, Japan, Apr. 13-15, 2015. |
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102級 |
廖少祺 |
1. Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao, “A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism,” IEEE Access, Vol. 8, pp. 114842-114853, June 2020. 5-year Impact Factor: 4.076
2. Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, and Tung-Chi Wu, “Imprecise 4-2 Compressor Design Used in Image Processing Applications,” IET Circuits, Devices & Systems, Vol. 13, No. 6, pp. 848-856, Sep. 2019. 5-year Impact Factor: 1.319
3. Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “An Imprecise 4-2 Compressor Design with Low Error Rate,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21), Yokohama, Japan, Apr. 18-20, 2018.
4. Yu-Cheng Cheng, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Pre-encoded Radix-4 Booth Multiplier,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIX), Yokohama, Japan, Apr. 20-22, 2016. |
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102級 |
林翊楓 |
1. Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, and Tung-Chi Wu, “Imprecise 4-2 Compressor Design Used in Image Processing Applications,” IET Circuits, Devices & Systems, Vol. 13, No. 6, pp. 848-856, Sep. 2019. 5-year Impact Factor: 1.319
2. Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “An Imprecise 4-2 Compressor Design with Low Error Rate,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21), Yokohama, Japan, Apr. 18-20, 2018.
3. Yi-Fong Lin, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A Novel Imprecise Compressor Design Used in DSP Multiplier,” in Proc. The 26th VLSI Design/ CAD Symposium, Hualien, Taiwan, Aug. 4-7, 2015. |
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103級 |
賴俊翔 |
1. Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, and Tung-Chi Wu, “Imprecise 4-2 Compressor Design Used in Image Processing Applications,” IET Circuits, Devices & Systems, Vol. 13, No. 6, pp. 848-856, Sep. 2019. 5-year Impact Factor: 1.319
2. Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Radix-4 Adder Design with Refined Carry,” in Proc. IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, Aug. 7-10, 2017, pp. 300-304.
3. Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A High-Speed Radix-4 Adder Design,” in Proc. The 28th VLSI Design/CAD Symposium, Kenting, Taiwan, Aug. 1-4, 2017. |
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107級 |
蕭焌壑 |
1. Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao, “A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism,” IEEE Access, Vol. 8, pp. 114842-114853, June 2020. 5-year Impact Factor: 4.076 |
碩專班
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學年度 |
研究生姓名 |
期刊與研討會論文 |
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101級 |
王彥淵 |
1. Yu-Cheng Cheng, Yen-Yuan Wang, and Yen-Jen Chang, “A Low Power Radix-4 Booth Multiplier with Precise Operand Exchange Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), Yokohama, Japan, Apr. 17-19, 2019. |
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104級 |
劉孟坤 |
1. 劉孟坤,林中義,張延任,陳育毅,“移動影像感知結合手機通訊軟體即時推播監視系統-以臺中區網中心機房應用為例”, TANET 2018 臺灣網際網路研討會, 2018.
2. 張雅嵐,陳仕豪,楊崇誠,呂仲聖,劉孟坤,林中義,張延任,陳育毅,“響應式網路氣象台結合 LINE 自動告警機制-以台中區網為例”, TANET 2017 臺灣網際網路研討會, 2017.
3. 陳仕豪,楊崇誠,葉宏,呂仲聖,劉孟坤,張延任,陳育毅,“使用 LINE 機器人(LINE BOT)之自動即時資安通報系統設計”, TANET 2017 臺灣網際網路研討會, 2017.
4. 劉孟坤,呂仲聖,陳仕豪,楊崇誠,張雅嵐,張延任,陳育毅,“建置虛擬桌面基礎架構（VDI）最佳資源配置及節能效率之探討”, TANET 2016 臺灣網際網路研討會, 2016. |
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