研究著作

Publications

Updated: 2025-05-12
期刊(Journal)
會議(Conference)
  • 1.
    Yen-Jen Chang, Kun-Lin Tsai, and Xu-Yao Chen, “Reconfigurable 9T Static RAM Design with Dynamic Switching between Content-Addressable Memory and In-Memory Computing,” IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), Early Access, May 2025.
    2.
    Yen-Jen Chang, Kun-Lin Tsai, Chun Cheng, and Xu-Yao Chen, “Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation,” IEEE Transactions on Circuits and Systems I (TCAS-I), Early Access, April 2025.
    3.
    Che-Hao Chang, Jason Lin, Jia-Wei Chang, Yu-Shun Huang, Ming-Hsin Lai, and Yen-Jen Chang, “Hybrid Deep Neural Networks with Multi-Tasking for Rice Yield Prediction Using Remote Sensing Data,” Agriculture-Basel, Vol. 14, April 2024.
    4.
    Yen-Jen Chang, Ming-Hsin Lai, Chien-Ho Wang, Yu-Shun Huang, and Jason Lin, “Target-Aware Yield Prediction (TAYP) Model Used to Improve Agriculture Crop Productivity,” IEEE Transactions on Geoscience and Remote Sensing (TGRS), Vol. 62, March 2024.
    5.
    Yen-Jen Chang, Yi-Da Wu, Yu-Lin Liao, Chien-Ho Wang, and Yen-Ching Wu, “Modified YOLO Network Model for Metaphase Cell Detection in Antinuclear Antibody Images,” ELSEVIER Engineering Applications of Artificial Intelligence (EAAI). Vol. 127, Part B, January 2024.
    6.
    Yen-Jen Chang, Kun-Lin Tsai, Wei-Cheng Jiang, and Meng-Kun Liu, “Content-Aware Malicious Webpage Detection using Convolutional Neural Network,” Springer US Multimedia Tools and Applications, January 2024, pp. 1-19.
    7.
    Yen-Jen Chang, and Shih-Hsiang Chen, “Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) , Vol. 13, No. 1, March 2023, pp. 371-381.
    8.
    Kun-Lin Tsai, Yen-Jen Chang, Chien-Ho Wang, and Cheng-Tse Chiang, “Accuracy- Configurable Radix-4 Adder with a Dynamic Output Modification Scheme,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 68, Issue 8, Aug. 2021, pp. 3328-3336.
    9.
    Yen-Jen Chang, Kun-Lin Tsai, and Yu-Cheng Cheng, “Data Retention based Low Leakage Power TCAM for Network Packet Routing,” IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Vol. 68, Issue 2, Feb. 2021, pp. 757-761.
    10.
    Yen-Jen Chang, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao, “A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism,” IEEE Access, Vol. 8, June 2020, pp. 114842-114853.
    11.
    Yen-Jen Chang, Kun-Lin Tsai, Yu-Cheng Cheng, and Meng-Rong Lu, “Low-Power Ternary Content-Addressable Memory Design Based on a Voltage Self-Controlled Fin Field-Effect Transistor Segment,” ELSEVIER Computers & Electrical Engineering, Vol. 81, Jan. 2020, pp.106528-106538.
    12.
    Yen-Jen Chang, Yu-Cheng Cheng, Yi-Fong Lin, Shao-Chi Liao, Chun-Hsiang Lai, and Tung-Chi Wu, “An Imprecise 4-2 Compressor Design Used in Image Processing Applications,” IET Circuits, Devices & Systems, Vol. 13, Issue 6, Oct. 2019, pp. 848-856.
    13.
    Yen-Jen Chang and Tung-Chi Wu, “Master-Slave Match Line Design for Low Power Content Addressable Memory,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI) , Vol. 23, No. 9, Sept. 2015, pp. 1740-1749.
    14.
    Kun-Lin Tsai, Yen-Jen Chang and Yu-Cheng Cheng, “Automatic Charge Balancing Content Addressable Memory with Self-control Mechanism,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 61, No. 10, Oct. 2014, pp. 2834-2841.
    15.
    Yen-Jen Chang and Hsiang-Yu Lu, “Improving the Performance of Port Range Check for Network Packet Filter,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 19, No. 1, Dec. 2013, pp. 3:1-3:21.
    16.
    Yen-Jen Chang, Kun-Lin Tsai, and Hsiang-Jen Tsai, “Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 60, No. 6, June 2013, pp. 1478-1486.
    17.
    Chuen-Horng Lin, Der-Chen Huang, Yung-Kuan Chan, Kai-Hung Chen, and Yen-Jen Chang, “Fast Color-Spatial Feature Based Image Retrieval Methods,” Expert Systems with Applications, Vol. 38, No. 9, June 2011, pp. 11412-11420.
    18.
    Yen-Jen Chang, “Using Dynamic Power Source (DPS) Technique to Reduce TCAM Leakage Power,” IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 57, No. 11, Nov. 2010, pp. 888-892.
    19.
    Yen-Jen Chang, “Don’t-Care Gating (DCG) TCAM Design Used in Network Routing Table,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 11, Nov. 2010, pp. 1599-1607.
    20.
    Yen-Jen Chang, “A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup,” IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 56, No. 6, June 2009, pp. 479-483.
    21.
    Yen-Jen Chang, “90-nm TCAM Cell Design with Leakage Suppression Technique,” IEE Electronics Letters, Vol. 45, No. 6, March 2009, pp. 300-302.
    22.
    Yen-Jen Chang and Yuan-Hong Liao, “Hybrid-Type CAM Design for Both Power and Performance Efficiency”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 16, No. 8, Aug. 2008, pp. 965-974.
    23.
    Yen-Jen Chang, “Two-Layer Hierarchical Matching Method for Energy-Efficient CAM Design,” IEE Electronics Letters, Vol. 43, No. 2, Jan. 2007, pp. 80-82.
    24.
    Yen-Jen Chang and Maofeng Lan, “Two New Techniques Integrated for Energy- Efficient TLB Design”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15, No. 1, Jan. 2007, pp. 13-23.
    25.
    Yen-Jen Chang, “An Energy-Efficient BTB Lookup Scheme for Embedded Processors”, IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 9, Sept. 2006, pp. 817-821.
    26.
    Yen-Jen Chang and Feipei Lai, “Dynamic Zero-Sensitivity Scheme for Low Power Cache Memories”, IEEE Micro, Vol. 25, Issue 4, July-Aug. 2005, pp. 20-32.
    27.
    Yen-Jen Chang, Feipei Lai and Chia-Lin Yang, “Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 12, No. 8, Aug. 2004, pp. 827-836.
    28.
    Yen-Jen Chang, Shanq-Jang Ruan and Feipei Lai, “Design and Analysis of Low Power Cache using Two-Level Filter Scheme”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 11, No. 4, Aug. 2003, pp. 568-580.
    29.
    Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn, "ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 10, No. 06, December 2002, pp. 942-949.
    30.
    Yen-Jen Chang, “Study of an efficient simulation method”, IEE Proceedings-Computers and Digital Techniques, Vol. 146, Issue 05, September 1999, pp. 253-258.
  • 1.
    Ci-Wun Jhong, Yen-Jen Chang and Hao-Wei Lu, “Low-Power Booth Multiplier Design for CNN Applications,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 28), Tokyo, Japan, Apr. 16-18, 2025.
    2.
    Wei-Ting Chang, and Yen-Jen Chang, “Single-Ended Write 10T SRAM Cell Design for In-Memory Computing,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 26), Tokyo, Japan, Apr. 19-21, 2023.
    3.
    Chun-Huo Hsiao, Chien-Ho Wang, and Yen-Jen Chang, “Low Power Approximate Booth Multiplier with Novel Encoding and Pre-Encoded Mechanism,” 32nd VLSI Design/CAD Symposium, Virtual, Taiwan, Aug. 3-6, 2021.
    4.
    Yen-Jen Chang, Kun-Lin Tsai, and Meng-Kun Liu, “A Real-Time Malicious Web Detection using Modified CNN,” 4th International Symposium on Mobile Internet Security (MobiSec 2019), Taichung, Taiwan, Oct. 17-19, 2019.
    5.
    Yu-Cheng Cheng, Yen-Yuan Wang, and Yen-Jen Chang, “A Low Power Radix-4 Booth Multiplier with Precise Operand Exchange Technique,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22), Yokohama, Japan, Apr. 17-19, 2019.
    6.
    Yu-Cheng Cheng, Yi-Fong Lin, Shao-ChiLiao, Tung-Chi Wu, and Yen-Jen Chang, “An Imprecise 4-2 Compressor Design with Low Error Rate,” in Proc. IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21), Yokohama, Japan,Apr. 18-20, 2018.
    7.
    Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Radix-4 Adder Design with Refined Carry,” IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, Aug. 7-10, 2017, pp. 300-304.
    8.
    Chun-Hsiang Lai, Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “A High-Speed Radix-4 Adder Design,” The 28th VLSI Design/CAD Symposium, Pingtung, Taiwan, Aug. 1-4, 2017.
    9.
    Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Mask Vertical Control TCAM for Network Router,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju, Korea, Oct. 25-28, 2016, pp. 469-472.
    10.
    Yu-Cheng Cheng, Shao-Chi Liao, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Pre-encoded Radix-4 Booth Multiplier,” IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XIX, Yokohama, Japan, April 20-22, 2016.
    11.
    Yi-Fong Lin, Yu-Cheng Cheng, Tung-Chi Wu and Yen-Jen Chang, “A Novel Imprecise Compressor Design Used in DSP Multiplier,” The 26th VLSI Design/ CAD Symposium, Taiwan, August 4-7, 2015.
    12.
    Yu-Cheng Cheng, Jin-Hao Chen, Tung-Chi Wu, and Yen-Jen Chang, “Low Leakage Router Design Using Vertical Gating Technique,” IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XVIII, Yokohama, Japan, April 13-15, 2015.
    13.
    Ya-chun Lin, Yen-Jen Chang, and Tung-Chi Wu, “Low-Power Content-Addressable Memory Design Using a Double Match-Line (DML) Architecture”, IEEE 56th International Midwest Symposium on Circuits & Systems, Ohio, August 4-7, 2013, pp. 425-428.
    14.
    Yu-Cheng Cheng, Tung-Chi Wu, and Yen-Jen Chang, “Charge Balance Tag Memory Design Used in TLB,” IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XVI, Yokohama, Japan, April 17-19, 2013.
    15.
    Guan-Lin Jiang, Tung-Chi Wu, and Yen-Jen Chang, “Low Power Multiplier with Alternative Bypassing Implementation,” International Conference on Embedded Systems and Applications (ESA’12), Las Vegas, Nevada, USA, July 16-19, 2012, pp. 77-82.
    16.
    Shuang-An Tseng, Tung-Chi Wu, and Yen-Jen Chang, “A Low Power SRAM Design with Segmented Stacking Technique,” IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XV, Yokohama, Japan, April 18-20, 2012.
    17.
    Guan-Lin Jiang, and Yen-Jen Chang, “A New Bypassing Design for Low Power Multiplier”, VLSI Design/ CAD Symposium, Taiwan, August 1-4, 2011, pp. 129-132.
    18.
    Hsin-Chun Liu, and Yen-Jen Chang, “A Low Power Radix-4 Booth Multiplier Design”, VLSI Design/ CAD Symposium, Taiwan, August 1-4, 2011, pp. 432-435.
    19.
    Yen-Jen Chang, and Tung-Chi Wu, “A low-power TCAM design using mask-aware match-line (MAML) technique”, ACM Great Lakes Symposium on VLSI 2011 (GLSVLSI 2011), Lausanne, Switzerland, May 2-4, 2011, pp. 109-114.
    20.
    Shao-Wei Huang, and Yen-Jen Chang, “A Full Parallel Priority Encoder Design Used in Comparator”, IEEE International Midwest Symposium on Circuits & Systems, Seattle, Washington, August 1-4, 2010, pp. 877-880.
    21.
    Hsiang-Yu Lu, and Yen-Jen Chang, “A High Performance Range Matching Circuit Design for Packet Filter”, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XIII, Yokohama, Japan, April 14-16, 2010, pp. 183.
    22.
    Hsiang-Jen Tsai, and Yen-Jen Chang, “Low Power Ternary CAM (TCAM) Design Using Mask Gating,” IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009), Delft, Netherlands, Sept. 9-11, 2009.
    23.
    Yen-Ting Chiang, and Yen-Jen Chang, “A New SRAM Cell Design for Both Power and Performance Efficiency,” IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2009), Hsinchu, Taiwan, Aug. 31-Sept. 2, 2009, pp. 13-19.
    24.
    Jin-Wei Yang, and Yen-Jen Chang, “Low Power Selected Gating Frame Buffer (SGFB) Design,” International Conference on Embedded Systems and Applications (ESA’09), Las Vegas, Nevada, USA, July 13-16, 2009, pp. 140-145.
    25.
    Yung-Feng Cheng, and Yen-Jen Chang, “A Novel High Performance Ternary CAM (TCAM) For LPM,” International Conference on Embedded Systems and Applications (ESA’09), Las Vegas, Nevada, USA, July 13-16, 2009, pp. 22-27.
    26.
    Yen-Jen Chang, “A Low-Leakage Routing Table Design”, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips) XII, Yokohama, Japan, April 15-17, 2009, pp. 167.
    27.
    Yen-Jen Chang, “Exploiting Frequent Opcode Locality for Power Efficient Instruction Cache”, ACM 18th Great Lakes symposium on VLSI (GLSVLSI 2008), Orlando, Florida, USA, May 4-6, 2008, pp. 399-402.
    28.
    Yen-Jen Chang, Yuan-Hong Liao and Shanq-Jang Ruan, “Improve CAM Power Efficiency Using Decoupled Match Line Scheme”, IEEE/ACM Design, Automation and Test in Europe (DATE 2007), April 16-20, 2007, pp. 1-6.
    29.
    Yen-Jen Chang, “An Ultra Low-Power TLB Design”, IEEE/ACM Design, Automation and Test in Europe (DATE 2006), March 6-10, 2006, pp. 1-6.
    30.
    Yen-Jen Chang, “Lazy BTB: Reduce BTB Energy Consumption Using Dynamic Profiling,” IEEE/ACM 11th Asia and South Pacific Design Automation Conference (ASP-DAC 2006), Jan. 24-27, 2006, pp. 917-922.
    31.
    Yen-Jen Chang, “An Alternative Real-Time Filter Scheme to Block Buffering,” IEEE/ACM 19th International Conference on VLSI Design (VLSI Design 2006), Jan. 3-7, 2006, pp. 762-765.
    32.
    Yen-Jen Chang, “A New Register Design for Low Power TLB and Cache,” IEEE 23th NORCHIP Conference, Nov. 21-22, 2005, pp. 1-4.
    33.
    Yen-Jen Chang, Yung-Ching Weng and Feipei Lai, “Enhanced Object Management for High Performance Web Proxy”, ACM Symposium on Applied Computing (SAC 2004), March 14-17, 2004, pp. 1711-1716.
    34.
    Yen-Jen Chang, Chia-Lin Yang and Feipei Lai, “Value-Conscious Cache: Simple Technique for Reducing Cache Access Power”, IEEE/ACM Design, Automation and Test in Europe (DATE 2004), Feb. 16-20, 2004, pp. 16-21.
    35.
    Yen-Jen Chang, Chia-Lin Yang and Feipei Lai, “A Power-Aware SWDR Cell for Reducing Cache Write Power,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2003), Aug. 25-27, 2003, pp.14-17.
    36.
    Yen-Jen Chang, Feipei Lai and Shanq-Jang Ruan, “Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost,” IEEE International Conference on Computer Design (ICCD 2002), Freiburg, Germany, September 16-18, 2002, pp. 334-339.
    37.
    Yen-Jen Chang and Feipei Lai, “Paged Cache: An Efficient Partition Architecture for Reducing Power,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), October 28-31, 2002, Vol. 2, pp. 473-478.
    38.
    Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai, "Energy Analysis of Bipartition Architecture for Pipelined Circuits" in proceeding of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Oct. 28-31, 2002, Vol. 2, pp. 7-12.
    39.
    Yen-Jen Chang, Feipei Lai and Shanq-Jang Ruan, “An Efficient Two-Level Filter Scheme for Low Power Cache,” IEEE/ACM 11th International Workshop on Logic & Synthesis (IWLS 2002), New Orleans, Louisiana, June 4-7, 2002, pp.61-66.
    40.
    Yen-Jen Chang, Feipei Lai and Shanq-Jang Ruan, “Sentry Tag: An Efficient Filter Scheme for Low Power Cache”, 7th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2002), Melbourne, Australia, 2002, pp. 135-140.
    41.
    Yen-Jen Chang and Feipei Lai, “Improve Web Proxy Performance by Alleviating Disk I/O Overhead,” International Computer Symposium (ICS 2002), Dec. 18-21, 2002, pp. 477-484.